In the semiconductor industry, there is a continuing trend toward higher device densities. To achieve these high densities, there has been and continues to be efforts toward scaling down device dimensions (e.g., at submicron levels) on semiconductor wafers. In order to accomplish such high device packing density, smaller and smaller feature sizes are required in integrated circuits (ICs) fabricated on small rectangular portions of the wafer, commonly known as dies. This can include width and spacing of interconnecting lines, spacing and diameter of contact holes, surface geometry such as corners and edges of various features as well as surface geometry of other features. To scale down device dimensions, more precise control of fabrication processes are required. The dimensions of and between features can be referred to as critical dimensions (CDs). Reducing CDs, and reproducing more accurate CDs facilitates achieving higher device densities through scaled down device dimensions and increased packing densities.
Manufacturing semiconductors or ICs typically includes numerous processes (e.g., exposing, baking, developing), during which hundreds of copies of an integrated circuit can be formed on a single wafer, and more particularly on each die of a wafer. In many of these steps, material is overlayed or removed from existing layers at specific locations to form desired circuit structures or elements. Generally, the manufacturing process involves creating several patterned layers on and into a substrate that ultimately forms the complete integrated circuit. This layering process creates electrically active regions in and on the semiconductor wafer surface. Layer to layer alignment and isolation of such electrically active regions can affect precision of structures formed on a wafer. If layers are not aligned within acceptable tolerances, overlay errors can compromise performance of electrically active regions and adversely affecting chip reliability.
Conventional overlay metrology systems and/or methodologies facilitate determining whether two layers lie within the acceptable tolerances. Misalignment can be caused by variations in a lithography process, such as stepper stage variations, lens variations, resist application, develop variations, wafer non-uniformities, etc. Measurements obtained via an overlay metrology tool are utilized to quantify magnitude of error and verify that such magnitude of error decreases as processes are adjusted.
There are two main functions of overlay metrology regarding fabrication of ICs: monitoring performance of lithographic alignment procedure(s) and assisting in setup of a lithography process. For example, overlay metrology can be utilized with a sample wafer to assess overlay performance of a wafer lot. Moreover, overlay measurements can be utilized to optimally configure a stepper system prior to operation, and can later be employed to maintain optimal stepper performance via periodic overlay evaluation.
Overlay error has typically been measured and analyzed only between adjacent layers. Turning now to the drawings, FIG. 1 illustrates a prior art method 100 of measuring overlay error. As a first layer is added to a wafer, a square layer 102 utilized as a portion of an overlay target 104 is created outside of IC design areas at various positions on the wafer. As a second layer is added to the wafer, a smaller second square layer 106 utilized as a portion of the overlay target 104 corresponding to the second layer of the IC is placed atop the first portion 102 of the overlay target 104, and a larger layer 108 utilized as a portion of a second overlay target 110 likewise corresponding to the second layer of the wafer is created (e.g., dashed lines indicate layers of overlay targets representing a same layer of the wafer). As a third layer of the wafer is created atop the second layer of the wafer, a smaller layer 112 utilized as a portion of the second overlay target 110 is placed on the larger second layer 108 of the overlay target 110. A larger third layer 114 utilized as a portion of an overlay target 116 is also created. The process continues until a pre-determined amount of layers have been created. Thus the layers 102, 106, 108, 112, and 114 enable measurement of overlay error (e.g., distance between center points of the overlay targets and rotational difference between such targets) between the first and second layers and the second and third layers, respectively. If overlay error between adjacent layers is below a pre-defined threshold tolerance, the process(es) creating the layers are deemed satisfactory.
However, in ICs with multiple layers, repeated overlay error(s) (even slight error(s)) between multiple layers can result in compromised performance of a completed IC. Turning briefly to FIG. 2, an acceptable overlay error 200 that can occur between two overlay targets is illustrated. Overlay target 202 corresponds to a first layer of an IC, and overlay target 204 corresponds to a second layer of an IC, wherein the overlay target 202 has a desirable width of d1 and the overlay target 204 has a desirable width of d2. As illustrated by dashed lines 206 and 208, variations in a process are accounted for via permitting the overlay target 202 to have a width as small as d3 and the overlay target 204 to have a width as large as d4. In conventional overlay metrology methods, intersection of the dashed lines 206 and 208 indicate an unacceptable overlay between two layers corresponding to the overlay targets 202 and 204. A distance d5 indicates an amount of overlay error between layers represented by overlay targets 202 and 204 (e.g., distance between center points of the overlay targets 202 and 204). Moreover, a rotation of α between such overlay targets 202 and 204 is also acceptable provided that the rotation α is below a pre-defined threshold. If the overlay targets 202 and 204 indicate an unacceptable amount of overlay error and/or rotation between two layers corresponding to the overlay targets 202 and 204, corrective measures can be taken regarding such two layers.
Turning now to FIG. 3, a plurality of IC devices and/or layers of a wafer 300 are illustrated, wherein the overlay error exemplified in FIG. 2 is repeated throughout such plurality of IC devices and/or layers 300. For example, the overlay error 200 (FIG. 2) exists between IC device 302 and IC device 304, wherein the IC devices 302 and 304 are located within adjacent layers. A substantially similar overlay error exists between IC devices 304 and 306, 306 and 308, 308 and 310, and 310 and 312. If fabrication device(s) and/or process(es) causing such overlay error 200 are not modified to mitigate such overlay errors, a large aggregated discrepancy results between non-adjacent devices in non-adjacent layers. For example, the device 312 is significantly rotated and displaced through a plurality of layers from device 302, while such devices 302 and 312 would ideally be approximately concentric. Such substantial rotation and displacement between layers and/or devices can compromise IC performance. Thus, a more robust overlay metrology system and/or methodology to analyze multiple layers of an IC and correct overlay error between such layers is desirable to mitigate the aforementioned deficiencies of conventional systems and/or methods.